MCQ of Computer Organization and Architecture with Answer set-3

1. An exception condition in a computer system caused by an event external to the CPU is called ........

A) Interrupt

B) Halt

C) Wait

D) Process

2. When the CPU detects an interrupt, it then saves its .............

A) Previous State

B) Next State

C) Current State

D) Both A and B

English: A photo of three 32-bit PCI slots. (Photo credit: Wikipedia)

3. A microprogram is sequencer perform the operation...

A) read

B) write

C) read and write

D) read and execute

4. A computer program that converts an entire program into machine language at one time is called

A) interpreter

B) simulator

C) compiler

D) commander

5. The unit which decodes and translates each instruction and generates the necessary enable signals for ALU and other units is called ..

A) arithmetic unit

B) logical unit

C) control unit

D) CPU

6. State whether the following statement is True or False for cache memory.

i) Cache memories are high-speed buffers which are inserted between the processors and main memory.

ii) They can also be inserted between main memory and mass storage.

iii) It can be used as secondary memory.

A) i- True, ii- False, iii-True

B) i- False, ii- True, iii-True

C) i-True, ii-True, iii-False

D) i- False, ii- False, iii-True

7. The channel which handles the multiple requests and multiplexes the data transfers from these devices a byte at a time is known as .....

A) multiplexor channel

B) the selector channel

C) block multiplex channel

D) both A and C

8. The address mapping is done, when the program is initially loaded is called ......

A) dynamic relocation

B) relocation

C) static relocation

D) dynamic as well as static relocation

9. State whether the following statement is True or False for PCI bus.

i) The PCI bus tuns at 33 MHZ and can transfer 32-bits of data(four bytes) every clock tick.

ii) The PCI interface chip may support the video adapter, the EIDE disk controller chip and may be two external adapter cards.

iii) PCI bus deliver the different throughout only on a 32-bit interface that other parts of the machine deliver through a 64-bit path.

A) i- True, ii- False, iii-True

B) i- False, ii- True, iii-True

C) i-True, ii-True, iii-False

D) i- False, ii- False, iii-True

10. The I/O processor has a direct access to ....................... and contains a number of independent data channels.

A) main memory

B) secondary memory

C) cache

D) flash memory